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general description the max13000e?ax13005e 6-channel level transla- tors provide the level shifting necessary to allow data transfer in multivoltage systems. externally applied volt- ages, v cc and v l , set the logic levels on either side of the device. lo gic signals present on the v l side of the device appear as higher voltage logic signals on the v cc side of the device, and vice-versa. the max13000e?ax13005e feature a low v cc and v l quiescent supply current less than 4?. the max13000e?ax13005e also have ?5kv esd protec- tion on the i/o v cc side for greater protection in applica- tions that route signals externally. the esd protection is specified using the human body model (hbm). the max13000e/max13001e/max13002e operate at a guar- anteed 230kbps data rate. the max13003e/ max13004e/max13005e operate at a guaranteed 20mbps data rate when v cc > +1.65v. the max13000e/max13003e are bidirectional level translators, allowing data translation in either direction (v l ? v cc ) on any single data line without a direction input. the max13001e/max13002e/max13004e/ max13005e unidirectional level translators level shift data in one direction (v l v cc or v cc v l ) on any single data line. the max13001e/max13002e/ max13004e/max13005e unidirectional translators inputs have the capability to interface with both cmos and open-drain (od) outputs. for more information see the ordering information, selector guide, and the input- driver requirements sections. the max13000e?ax13005e operate with +0.9v to +3.6v v l voltages and +1.5v to +3.6v v cc voltages. the max13000e?ax13005e are available in 16-bump ucsp ? and 16-pin tssop packages, and are specified over the extended -40 c to +85 c operating tempera- ture range. applications cmos logic-level translation open-drain i/o translation od-to-cmos signal conversion low-voltage asic level translation cell phones spi and microwire level translation smart-card readers portable pos systems portable communication devices low-cost serial interfaces telecommunications equipment features ? guaranteed data-rate options 230kbps (max13000e/max13001e/max13002e) 20mbps (max13003e/max13004e/max13005e) ? bidirectional level translation without a direction input ? operational down to +0.9v on v l and +1.5v on v cc ? 15kv esd protection on i/o v cc lines per hbm ? low <4a quiescent current ? enable/shutdown control ? 2mm x 2mm, 16-bump ucsp and lead packaging options ? cmos or open-drain outputs interface capability max13000e?ax13005e ultra-low-voltage level translators ________________________________________________________________ maxim integrated products 1 bottom view max13000e/max13003e 4 x 4 ucsp v cc gnd i/ov cc 5 i/ov cc 4 i/ov cc 3 1 d c b a 234 i/ov cc 1 i/ov cc 2 i/ov l 2 i/ov cc 6 i/ov l 1 i/ov l 5 i/ov l 6 i/ov l 3v l en i/ov l 4 pin configurations 19-3692; rev 0; 6/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ucsp is a trademark of maxim integrated products, inc. spi is a trademark of motorola, inc. microwire is a trademark of national semiconductor corp. typical operating circuits and selector guide appear at end of data sheet. ordering information continued at end of data sheet. ordering information part temp range pin- package max13000e eue -40? to +85? 16 tssop pin configurations continued at end of data sheet.
max13000e?ax13005e ultra-low-voltage level translators 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +1.5v to +3.6v, v l = +0.9v to v cc , c i/ovl 15pf, c i/ovcc 50pf, t a = -40? to +85?, unless otherwise noted. typical val- ues are at t a = +25?.) (notes 1, 4) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltages referenced to gnd. v cc ...........................................................................-0.3v to +4v v l ..............................................................................-0.3v to +4v i/o vcc_ .......................................................-0.3v to (v cc + 0.3v) i/o vl_ ............................................................-0.3v to (v l + 0.3v) en .................................................................-0.3v to (v l + 0.3v) short-circuit duration i/o vl_ , i/o vcc_ to gnd ..........continuous continuous power dissipation (t a = +70?) 16-pin tssop (derate 9.4mw/? at +70?) ................755mw 16-bump ucsp (derate 8.2mw/? at +70?) .............659mw operating temperature range ..........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units v l supply range v l v l v cc (note 2) 0.9 v cc v v cc supply range v cc (note 2) 1.5 3.6 v t a = +25 c4 supply current from v cc (note 3) i qvcc t a = +85 c40 ? (note 3) 1 5 t a = +25 c v l < v cc - 0.2v 2 (note 3) 4 40 supply current from v l (note 3) i qvl t a = +85 c v l < v cc - 0.2v 20 ? en = gnd, t a = +25 c2 v cc shutdown supply current (note 3) i shdn-vcc en = gnd, t a = +85 c20 ? v l < v cc - 0.2v, en = gnd 2 t a = +25 c en = gnd 1 4 v l < v cc - 0.2v, en = gnd 20 v l shutdown supply current (note 3) t a = +85 c en = gnd 40 ? t a = +25 c 0.35 i/o tri-state output leakage current i/o v l_ , i/o v cc_ , en = gnd t a = +85 c1 ? t a = +25 c 0.2 i/o tri-stated output leakage current v l < v cc - 0.2v, i/o v l_ , i/o v cc_ , en = gnd t a = +85 c 0.5 ? t a = +25 c 0.35 en input leakage current t a = +85 c1 ?
max13000e?ax13005e ultra-low-voltage level translators _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +1.5v to +3.6v, v l = +0.9v to v cc , c i/ovl 15pf, c i/ovcc 50pf, t a = -40? to +85?, unless otherwise noted. typical val- ues are at t a = +25?.) (notes 1, 4) parameter symbol conditions min typ max units logic-level thresholds i/ov l_ input-voltage-high threshold v ihl 2/3 v l v i/ov l_ input-voltage-low threshold v ill 1/3 v l v i/ov cc_ input-voltage-high threshold v ihc 2/3 v cc v i/ov cc_ input-voltage-low threshold v ilc 1/3 v cc v en input-voltage-high threshold v ihen 2/3 v l v en input-voltage-low threshold v ilen 1/3 v l v i/ov l_ output-voltage high v ohl i/ov l_ source current = 20? v l - 0.25 v max13002e/max13005e, ov l_ sink current = 1? 0.3 i/ov l_ output-voltage low v oll max13000e/max13001e/max13003e/ max13004e, i/ov l_ sink current = 20? 0.25 v i/ov cc_ output-voltage high v ohc i/ov cc_ source current = 20? v cc - 0.25 v max13001e/max13004e, ov cc_ sink current = 1? 0.3 i/ov cc_ output-voltage low v olc max13000e/max13002e/max13003e/ max13005e, i/ov cc_ sink current = 20? 0.25 v output currents v cc = +1.65v, max13003e/max13004e/max13005e 25 output sink current during transient (v cc side) v cc = +1.65v, max13000e/max13001e/max13002e 1 ma v l = +1.2v, v cc = +1.65v, max13003e/max13004e/max13005e 30 output sink current during transient (v l side) v l = +1.2v, v cc = +1.65v, max13000e/max13001e/max13002e 1 ma
max13000e?ax13005e ultra-low-voltage level translators 4 _______________________________________________________________________________________ electrical characteristics (continued) (v cc = +1.5v to +3.6v, v l = +0.9v to v cc , c i/ovl 15pf, c i/ovcc 50pf, t a = -40? to +85?, unless otherwise noted. typical val- ues are at t a = +25?.) (notes 1, 4) parameter symbol conditions min typ max units v cc = +1.65v, max13003e/max13004e/max13005e 22 output source current during transient (v cc side) v cc = +1.65v, max13000e/max13001e/max13002e 1 ma v l = +1.2v, v cc = +1.65v, max13003e/max13004e/max13005e 25 output source current during transient (v l side) v l = +1.2v, v cc = +1.65v, max13000e/max13001e/max13002e 1 ma esd protection human body model 15 air-gap discharge (iec61000-4-2) 10 i/ov cc_ contact discharge (iec61000-4-2) 8 kv timing characteristics (v cc = +1.5v to +3.6v, v l = +0.9v to v cc , c i/ovl 15pf, c i/ovcc 50pf, t a = -40? to +85?, unless otherwise noted. typical val- ues are at t a = +25?.) (notes 1, 4) parameter symbol conditions min typ max units c i/ovcc = 50pf, max13003e/max13004e/max13005e, v cc = +1.65v, figures 1a, 1b 15 c i/ovcc = 50pf, max13003e/max13004e/max13005e, v cc = +1.5v, figures 1a, 1b 15 i/ov cc_ rise time t rvcc c i/ovcc = 50pf, max13000e/max13001e/max13002e, figures 1a, 1b 400 1400 ns c i/ovcc = 50pf, max13003e/max13004e/max13005e, v cc = +1.65v, figures 1a, 1b 15 c i/ovcc = 50pf, max13003e/max13004e/max13005e, v cc = +1.5v, figures 1a, 1b 15 i/ov cc_ fall time t fvcc c i/ovcc = 50pf, max13000e/max13001e/max13002e, figures 1a, 1b 400 1400 ns
max13000e?ax13005e ultra-low-voltage level translators _______________________________________________________________________________________ 5 timing characteristics (continued) (v cc = +1.5v to +3.6v, v l = +0.9v to v cc , c i/ovl 15pf, c i/ovcc 50pf, t a = -40? to +85?, unless otherwise noted. typical val- ues are at t a = +25?.) (notes 1, 4) parameter symbol conditions min typ max units c i/ovl = 50pf, max13003e/max13004e/max13005e, v cc = +1.65v, figures 2a, 2b 15 c i/ovl = 15pf, max13003e/max13004e/max13005e, v cc = +1.5v, figures 2a, 2b 15 i/ov l_ rise time t rvl c i/ovl = 50pf, max13000e/max13001e/max13002e, figures 2a, 2b 300 1200 ns c i/ovl = 50pf, max13003e/max13004e/max13005e, v cc = +1.65v, figures 2a, 2b 15 c i/ovl = 15pf, max13003e/max13004e/max13005e, v cc = +1.5v, figures 2a, 2b 15 i/ov l_ fall time t fvl c i/ovl = 50pf, max13000e/max13001e/max13002e, figures 2a, 2b 300 1200 ns c i/ovcc = 50pf, max13003e/max13004e/max13005e, figures 1a, 1b 20 propagation delay (driving i/ov l_ ) i/o vl-vcc c i/ovcc = 50pf, max13000e/max13001e/max13002e, figures 1a, 1b 1000 ns v cc > +1.65v, c i/ovl = 50pf, max13003e/max13004e/max13005e, figures 2a, 2b 20 v cc = 1.5v, c i/ovl = 15pf, max13003e/max13004e/max13005e, figures 2a, 2b 20 propagation delay (driving i/ov cc_ ) i/o vcc-vl c i/ovl = 50pf, max13000e/max13001e/max13002e, figures 2a, 2b 1000 ns c i/ovcc = 50pf, cmos output, figure 3 2 propagation delay from i/ov l to i/ov cc_ after en (note 5) t en-vcc c i/ovcc = 50pf, od output, figure 3 6 ?
typical operating characteristics (v cc = +3.3v, v l = +0.9v, t a = +25?, max13003e.) 0.1 1 10 100 1000 v l supply current vs. supply voltage (driving i/o v l , v l = 0.9v) max13000etoc01 supply voltage (v) v l supply current ( a) 1.5 2.4 2.7 1.8 2.1 3.0 3.3 3.6 data rate = 20mbps data rate = 230kbps v l supply current vs. supply voltage (driving i/o v cc , v l = 0.9v) max13000etoc02 supply voltage (v) v l supply current (ma) 3.3 3.0 2.7 2.4 2.1 1.8 0.01 0.1 1 0.001 1.5 3.6 data rate = 20mbps data rate = 230kbps v cc supply current vs. supply voltage (driving i/o v l , v l = 0.9v) max13000etoc03 supply voltage (v) v cc supply current (ma) 3.3 3.0 2.7 2.4 2.1 1.8 0.1 1 10 0.01 1.5 3.6 data rate = 230kbps data rate = 20mbps max13000e?ax13005e ultra-low-voltage level translators 6 _______________________________________________________________________________________ timing characteristics (continued) (v cc = +1.5v to +3.6v, v l = +0.9v to v cc , c i/ovl 15pf, c i/ovcc 50pf, t a = -40? to +85?, unless otherwise noted. typical val- ues are at t a = +25?.) (notes 1, 4) parameter symbol conditions min typ max units c i/ovl = 50pf, cmos output, figure 4 2 propagation delay from i/ov cc to i/ov l after en (note 5) t en-vl c i/ovl = 50pf, od output, figure 4 6 ? each translator equally loaded, max13003e/max13004e/max13005e ? channel-to-channel skew t skew each translator equally loaded, max13000e/max13001e/max13002e ?50 ns part-to-part skew (note 6) t ppskew c i/ovl = 15pf, c i/ovcc = 15pf, v l = +1.8v, v cc = +2v, ? t = +5 c, max13003e/max13004e/max13005e 10 ns max13003e/max13004e/max13005e v cc > +1.65v, c i/ovl = 50pf, c i/ovcc = 50pf 20 mbps maximum data rate max13000e/max13001e/max13002e c i/ovl = 50pf, c i/ovcc = 50pf 230 kbps note 1: all devices are 100% production tested at t a = +25?. limits are guaranteed by design over the entire temperature range. note 2: v l must be less than or equal to v cc during normal operation. however, v l can be greater than v cc during startup and shutdown conditions. note 3: this consumption is referred to as no signal transmission. note 4: guaranteed by design with an input signal full swing, rise/fall time 3ns, source resistance is 50 ? . note 5: enable input signal full swing and rise/fall time 50ns. note 6: guaranteed by design, not production tested.
max13000e?ax13005e ultra-low-voltage level translators _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v cc = +3.3v, v l = +0.9v, t a = +25?, max13003e.) 0.001 0.01 0.1 1.0 10 v cc supply current vs. supply voltage (driving i/ov cc , v l = +0.9v) max13000etoc04 supply voltage (v) v cc supply current (ma) 1.5 2.4 2.7 1.8 2.1 3.0 3.3 3.6 data rate = 230kbps data rate = 20mbps v l supply current vs. temperature (driving i/ov cc , v cc = +3.3v, v l = +0.9v) max13000e toc05 temperature ( c) v cc supply current ( a) 60 35 10 -15 300 310 320 330 340 290 -40 85 data rate = 20mbps v cc supply current vs. temperature (driving i/ov cc , v cc = +3.3v, v l = +0.9v) max13000e toc06 temperature ( c) v cc supply current (ma) 60 35 10 -15 3.90 3.95 4.00 4.05 4.10 3.85 -40 85 data rate = 20mbps 0 40 20 80 60 120 100 140 10 30 40 20 50 60 70 80 90 100 v l supply current vs. capacitive load on i/o v cc (driving i/ov l , v cc = 3.3v, v l = +0.9v) max31000etoc07 capacitive load (pf) v l supply current ( a) data rate = 20mbps data rate = 230kbps 0 2 1 4 3 7 5 8 6 9 10 30 40 20 50 60 70 80 90 100 v cc supply current vs. capacitive load on i/o v cc (driving i/ov l , v cc = 3.3v, v l = +0.9v) max31000etoc08 capacitive load (pf) v cc supply current (ma) data rate = 20mbps data rate = 230kbps 0 2 1 4 3 7 5 8 6 9 10 30 40 20 50 60 70 80 90 100 rise/fall time vs. capacitive load on i/o v cc (driving i/ov l , v cc = 3.3v, v l = +0.9v) max31000etoc09 capacitive load (pf) rise/fall time (ns) t f t r 0 2 1 4 3 7 5 6 8 10 30 40 20 50 60 70 80 90 100 rise/fall time vs. capacitive load on i/o v l (driving i/ov cc , = 3.3v, v l = +0.9v) max31000etoc10 capacitive load (pf) rise/fall time (ns) t f t r 5.0 6.0 5.5 7.0 6.5 8.5 7.5 8.0 9.0 10 30 40 20 50 60 70 80 90 100 propagation delay vs. capacitive load on i/o v cc (driving i/ov l , v cc , = 3.3v, v l = +0.9v) max31000etoc11 capacitive load (pf) propagation delay (ns) 2.0 3.0 2.5 4.5 4.0 3.5 5.5 6.0 5.0 6.5 10 40 50 20 30 60 70 80 90 100 propagation delay vs. capacitive load on i/o v l (driving i/ov cc , v cc = 3.3v, v l = +0.9v) max13000etoc12 capacitive load (pf) propagation delay (ns)
max13000e?ax13005e ultra-low-voltage level translators 8 _______________________________________________________________________________________ rail-to-rail driving (driving i/ov l v cc = +3.3v, v l = +0.9v, c i/ovcc = 50pf, data rate = 4mbps) max31000etoc16 i/ov cc 2v/div gnd i/ov l_ 500mv/div gnd 40ns/div 0 6 4 2 1 5 3 7 8 9 10 11 12 13 100 8400 4250 12,550 16,700 20,850 25,000 v cc + v l supply current vs. frequency (driving i/ov l , v cc = +3.3v, v l = +0.9v) max31000etoc18 frequency (khz) v cc + v l supply current (ma) v cc + v l v l v cc i/ov l is driven with a 0.9v square wave 0 6 4 2 1 5 3 7 8 9 10 11 12 13 100 8400 4250 12,550 16,700 20,850 25,000 v cc + v l supply current vs. frequency (driving i/ov cc , v cc = +3.3v, v l = +0.9v) max31000etoc19 frequency (khz) v cc + v l supply current (ma) v cc + v l v l v cc i/ov cc is driven with a 3.3v square wave 0 1.5 1.0 0.5 2.0 2.5 3.0 020 15 5 10 253035404550 v ohl vs. i ohl for v l side (v cc = 3.3v) max13000etoc20 i ohl ( a) v ohl (v) v l = +2.5v v l = +1.8v v l = +0.9v 0 0.15 0.10 0.05 0.20 0.25 020 15 5 10 253035404550 v oll vs. i oll for v l side (v cc = 3.3v) max13000etoc21 i oll ( a) v oll (v) v l = +2.5v v l = +1.8v v l = +0.9v od rail-to-rail driving (max13005e) (driving i/ov l , v cc = +3.3v, v l = +0.9v, c i/ovcc = 56pf, data rate = 230mbps, r pullup = 1k ? ) max31000etoc13 i/ov cc 2v/div gnd i/ov l_ 500mv/div gnd 200ns/div od rail-to-rail driving (max13002e) (driving i/ov l , v cc = +3.3v, v l = +0.9v, c i/ovcc = 56pf, data rate = 230kbps, r pullup = 15k ? ) max31000etoc14 i/ov cc 2v/div gnd i/ov l_ 500mv/div gnd 2 s/div rail-to-rail driving (driving i/ov l , v cc = +3.3v, v l = +0.9v, c i/ovcc = 50pf, data rate = 230kbps) max31000etoc15 i/ov cc 2v/div gnd i/ov l_ 500mv/div gnd 1 s/div rail-to-rail driving (driving i/ov l , v cc = +3.3v, v l = +0.9v, c i/ovcc = 50pf, data rate = 20mbps) max31000etoc17 i/ov cc 2v/div gnd i/ov l_ 500mv/div gnd 10ns/div typical operating characteristics (continued) (v cc = +3.3v, v l = +0.9v, t a = +25?, max13003e.)
max13000e?ax13005e ultra-low-voltage level translators _______________________________________________________________________________________ 9 pin descriptions pin tssop ucsp name function 1 b1 i/ov l 1 cmos input/output 1, referenced to v l 2 b2 i/ov l 2 cmos input/output 2, referenced to v l 3 a1 i/ov l 3 cmos input/output 3, referenced to v l 4a2 v l logic input voltage, +0.9v v l v cc . bypass v l to gnd with a 0.1? capacitor. 5a3 en enable input. when en is pulled low, i/o v cc 1 to i/o v cc 6 and i/o v l 1 to i/o v l 6 are tri-stated. drive en high (v l ) for normal operation. 6 a4 i/ov l 4 cmos input/output 4, referenced to v l 7 b3 i/ov l 5 cmos input/output 5, referenced to v l 8 b4 i/ov l 6 cmos input/output 6, referenced to v l 9 c4 i/ov cc 6 cmos input/output 6, referenced to v cc 10 c3 i/ov cc 5 cmos input/output 5, referenced to v cc 11 d4 i/ov cc 4 cmos input/output 4, referenced to v cc 12 d3 gnd ground 13 d2 v cc v cc input voltage, +1.5v v cc 3.6v. bypass v cc to gnd with a 0.1? capacitor. for full esd protection, use a 1? bypass capacitor on v cc . 14 d1 i/ov cc 3 cmos input/output 3, referenced to v cc 15 c2 i/ov cc 2 cmos input/output 2, referenced to v cc 16 c1 i/ov cc 1 cmos input/output 1, referenced to v cc max13000e/max13003e 0 0.15 0.10 0.05 0.20 0.25 020 15 5 10 253035404550 v olc vs. i olc for v cc side max13000etoc22 i olc ( a) v olc (v) v cc = +2.5v v cc = +1.8v v cc = +3.3v 1.0 2.5 2.0 1.5 3.0 3.5 020 15 5 10 253035404550 v ohc vs. i ohc for v cc side max13000etoc23 i ohc ( a) v ohc (v) v cc = +3.3v v cc = +1.8v v cc = +2.5v typical operating characteristics (continued) (v cc = +3.3v, v l = +0.9v, t a = +25?, max13003e.)
max13000e?ax13005e ultra-low-voltage level translators 10 ______________________________________________________________________________________ pin tssop ucsp name function 1b1ov l 1 cmos output 1, referenced to v l 2b2ov l 2 cmos output 2, referenced to v l 3a1ov l 3 cmos output 3, referenced to v l 4a2 v l logic input voltage, +0.9v v l v cc . bypass v l to gnd with a 0.1? capacitor. 5a3 en enable input. when en is pulled low, ov cc 1 to ov cc 6 and iv l 1 to iv l 6 are tri-stated. drive en high (v l ) for normal operation. 6a4ov l 4 cmos output 4, referenced to v l 7b3ov l 5 cmos output 5, referenced to v l 8b4ov l 6 cmos output 6, referenced to v l 9c4iv cc 6 open-drain-compatible input 6, reference to v cc 10 c3 iv cc 5 open-drain-compatible input 5, referenced to v cc 11 d4 iv cc 4 open-drain-compatible input 4, referenced to v cc 12 d3 gnd ground 13 d2 v cc v cc input voltage, +1.5v v cc 3.6v. bypass v cc to gnd with a 0.1? capacitor. for full esd protection, use a 1? bypass capacitor on v cc . 14 d1 iv cc 3 open-drain-compatible input 3, referenced to v cc 15 c2 iv cc 2 open-drain-compatible input 2, referenced to v cc 16 c1 iv cc 1 open-drain-compatible input 1, referenced to v cc max13001e/max13004e pin descriptions (continued)
max13000e?ax13005e ultra-low-voltage level translators ______________________________________________________________________________________ 11 pin tssop ucsp name function 1b1 iv l 1 open-drain-compatible input 1, referenced to v l 2b2 iv l 2 open-drain-compatible input 2, referenced to v l 3a1 iv l 3 open-drain-compatible input 3, referenced to v l 4a2 v l logic input voltage, +0.9v v l v cc . bypass v l to gnd with a 0.1? capacitor. 5a3 en enable input. when en is pulled low, ov cc 1 to ov cc 6 and iv l 1 to iv l 6 are tri-stated. drive en high (v l ) for normal operation. 6a4 iv l 4 open-drain-compatible input 4, referenced to v l 7b3 iv l 5 open-drain-compatible input 5, referenced to v l 8b4 iv l 6 open-drain-compatible input 6, referenced to v l 9c4ov cc 6 cmos output 6, referenced to v cc 10 c3 ov cc 5 cmos output 5, referenced to v cc 11 d4 ov cc 4 cmos output 4, referenced to v cc 12 d3 gnd ground 13 d2 v cc v cc input voltage, +1.5v v cc 3.6v. bypass v cc to gnd with a 0.1? capacitor. for full esd protection, use a 1? bypass capacitor on v cc . 14 d1 ov cc 3 cmos output 3, referenced to v cc 15 c2 ov cc 2 cmos output 2, referenced to v cc 16 c1 ov cc 1 cmos output 1, referenced to v cc max13002e/max13005e pin descriptions (continued)
max13000e?ax13005e ultra-low-voltage level translators 12 ______________________________________________________________________________________ test circuits/timing diagrams figure 1a. driving i/ovl figure 1b. timing for driving i/ov l max13000e c i/ovcc en i/ov l_ r s source v l v cc i/ov cc unused i/os are grounded. 90% 50% 10% i/ov cc_ i/ov l_ t rise/fall i/o vl-vcc t rvcc t fvcc 90% 50% 10% i/o vl-vcc t rise/fall < 3ns (max13003e/max13004e/max13005e) t rise/fall < 80ns (max13000e/max13001e/max13002e) figure 2a. driving i/ov cc figure 2b. timing for driving i/ov cc max13000e c i/ovl en i/ov l_ r s source unused i/os are grounded. v l v cc i/ov cc 90% 50% 10% i/ov cc_ i/ov l_ t rise/fall i/o vcc-vl i/o vcc-vl t rvl t fvl 90% 50% 10% t rise/fall < 3ns (max13003e/max13004e/max13005e) t rise/fall < 80ns (max13000e/max13001e/max13002e)
max13000e?ax13005e ultra-low-voltage level translators ______________________________________________________________________________________ 13 test circuits/timing diagrams (continued) figure 3. propagation delay from i/ov l to i/ov cc after en max13000e c i/ovcc en i/ov l_ source i/ov cc max13000e c i/ovcc en i/ov l_ source v l i/ov cc en v l 0 v l v cc 0 0 i/ov l_ i/ov cc_ t' en-vcc en v l 0 v l v cc 0 0 i/ov l_ t en-vcc is which ever is larger between t' en-vcc and t" en-vcc . i/ov cc_ v cc / 2 t" en-vcc v cc / 2 figure 4. propagation delay from i/ov cc to i/ov l after en max13000e v cc en i/ov l_ source v l i/ov cc c i/ovl max13000e en i/ov l_ source v l i/ov cc c i/ovl en v l 0 v cc v l 0 0 i/ov cc_ i/ov l_ v l / 2 t' en-vl en v l 0 v cc v l 0 0 i/ov cc_ t en-vl is which ever is larger between t' en-vl and t" en-vl . i/ov l_ v l / 2 t" en-vl
max13000e?ax13005e detailed description the max13000e?ax13005e logic-level translators provide the level shifting necessary to allow data trans- fer in multivoltage systems. externally applied voltages, v cc and v l , set the logic levels on each side of the device. logic signals present on the v l side of the device appear as higher voltage logic signals on the v cc side of the device, and vice-versa. the max13000e/max13003e are bidirectional level translators allowing data translation in either direction (v l ? v cc ) on any single data line without the use of a direction input. the max13001e/max13002e/ max13004e/max13005e unidirectional level translators level shift data in one direction (v l v cc or v cc v l ) on any single data line. the max13001e/ max13002e/max13004e/max13005e unidirectional translators?inputs have the capability to interface with both cmos and open-drain (od) outputs. for more information, see the ordering information section and the input driver requirements section. the max13000e?ax13005e accept v l from +0.9v to +3.6v. all devices have v cc ranging from +1.5v to +3.6v, making them ideal for data transfer between low-voltage asics/plds and higher voltage systems. the max13000e?ax13005e feature low v cc quies- cent supply current of less than 4?, and v l quiescent supply current of less than 2? when in shutdown. the max13000e?ax13005e have ?5kv esd protection on the v cc side for greater protection in applications that route signals externally. the esd protection is specified using the human body model (hbm).the max13000e/max13001e/max13002e operate at a guaranteed 230kbps data rate. the max13003e/ max13004e/max13005e operate at a guaranteed 20mbps data rate when v cc > +1.65v. level translation for normal operation, ensure that +1.5v v cc +3.6v, and +0.9v v l v cc . during power-up sequencing, v l v cc does not damage the device whenever v l is within the absolute maximum ratings (see the absolute maximum ratings section). during power-supply sequencing, when v cc is floating and v l is powered up, 1ma of current can be sourced to each load on the v l side, yet the device does not latch up. the max13000e?ax13005e are designed to have v cc v l at all times; however, if v cc is turned off, the part will not be damaged and will not latch up. to pre- vent excessive leakage currents in either the i/o or supply lines, the i/o on the v l side must be left in the high state. the maximum data rate for the max13000e max13005e depends heavily on the load capacitance (see the typical operating characteristics ), output impedance of the driver, and the operational voltage range (see the timing characteristics table). open-drain operation the max13001e/max13002e/max13004e/max13005e have input stages specifically designed to accommo- date external open-drain drivers. when using open- drain drivers, the max13001e/max13002e/ max13004e/max13005e operate in a unidirectional- only mode, translating from the od side to the cmos side. for improved performance, the rise- and fall-time accelerators are present on both the cmos and the od side. see the input-driver requirement section. do not use pullup resistors greater than 15k ? for proper operation, and smaller pullup resistance may be need- ed for higher speed operation. input-driver requirements the max13000e?ax13005e feature four different architectures based on the speed of the part, as well as on whether the translator is a cmos-to-cmos transla- tor, or whether it is an od-to-cmos translator. 20mbps cmos-to-cmos bidirectional translator (max13003e) the max13003e architecture is based on a one-shot accelerator output stage (figure 5). accelerator output stages are always in tri-state, except when there is a transition on any of the translators on the input side, either i/ov l or i/ov cc . a short pulse is generated dur- ing which the one-shot output stage becomes active and charges/discharges the capacitances at the i/os. due to its bidirectional nature, the accelerator stages on both the i/ov cc and the i/ov l become active during an i/o transition from low to high or high to low. this can lead to some current feeding into the external source that is driving the translator. however, this behavior helps speed up the transition on the driven side. the type of devices that drive the inputs of the max13003e is usually specified with an output drive- current capability (i out ). when driving the inputs of the max13003e, the maximum achievable speed is con- strained by the drive current of the external driver. to insure the maximum possible throughput of 20mbps, the external driver should meet the following requirement: i out 1.67 10 8 v (c in + c p ) ultra-low-voltage level translators 14 ______________________________________________________________________________________
where, c p is the parasitic capacitance of the traces, v is the supply voltage of the driven side (i.e., v l or v cc ), and c in is the input capacitance of the driven side (c in = 10pf for v l side, c in = 20pf for v cc side). 20mbps od-to-cmos unidirectional translators (max13004e/max13005e) the max13004e/max13005e architecture is virtually the same as that for the bidirectional cmos-to-cmos trans- lators, the only difference being that the output inverter (inverter 4) at the driving side accommodates the driving capabilities of an open-drain output (figure 6). for proper operation, a pullup resistor needs to be con- nected from the open-drain output to the power supply of the driving side. use pullup resistors no larger than 15k ? . 230kbps cmos-to-cmos bidirectional translator (max13000e) the architecture of the max13000e lacks the one-shot accelerator output stages since the transitions that this device handles are limited by its data rate, 230kbps (figure 7). for proper operation, the driver must meet the following conditions: 1k ? maximum output impedance and 1ma minimum output current. 230kbps od-to-cmos unidirectional translators (max13001e/max13002e) the architecture of the max13001e/max13002e is simi- lar to that of the 230kbps cmos-to-cmos part, with the difference that it accommodates the driving capability of an open-drain output on the driving side, and also that it has only a single one-shot output stage (figure 8). for proper operation, a pullup resistor needs to be con- nected from the open-drain output to the power supply of the driving side. use pullup resistors no larger than 15k ? . figure 9 shows a graph of the typical input current ver- sus input voltage for all of the above configurations. enable output mode (en) the max13000e?ax13005e feature an enable (en) input. drive en low to set the max13000e?ax13005e i/os in tri-state mode. drive en high (v l ) for normal operation. ?5kv esd protection as with all maxim devices, esd-protection structures are incorporated on all pins to protect against electro- static discharges encountered during handling and assembly. the i/ov cc lines have extra protection against static discharge. maxim? engineers have developed state-of-the-art structures to protect these pins against esd of ?5kv without damage. the esd max13000e?ax13005e ultra-low-voltage level translators ______________________________________________________________________________________ 15 p one-shot v cc v l i/ov l i/ov cc 5k ? 5k ? inverter 3 inverter 4 inverter 2 inverter 1 n one-shot p one-shot n one-shot figure 5. architecture of 20mbps, cmos-to-cmos bidirectional translators
max13000e?ax13005e ultra-low-voltage level translators 16 ______________________________________________________________________________________ p one-shot v l/ v cc v cc/ v l iv cc /iv l ov l /ov cc 5k ? 75k ? inverter 4 5k ? inverter 3 n one-shot p one-shot n one-shot open-drain compatible input cmos- compatible input 20mbps open-drain-to-cmos unidirectional level translator inverter 1 inverter 2 figure 6. architecture of 20mbps, od-to-cmos unidirectional translators v cc v l i/ov l i/ov cc 5k ? 5k ? inverter 3 inverter 4 inverter 2 inverter 1 230kbps bidirectional cmos-to-cmos level translator figure 7. architecture of 230kbps, cmos-to-cmos bidirectional translator
max13000e?ax13005e ultra-low-voltage level translators ______________________________________________________________________________________ 17 structures withstand high esd in all states: normal operation, tri-state output mode, and power-down. after an esd event, maxim? e-versions keep working with- out latchup, whereas competing products can latch and must be powered-down to remove latchup. esd protection can be tested in various ways. the i/ov cc lines of the max13000e?ax13005e are char- acterized for protection to ?5kv using the human body model. esd test conditions esd performance depends on a variety of conditions. contact maxim for a reliability report that documents test setup, test methodology, and test results. human body model figure 10 shows the human body model and figure 11 shows the current waveform it generates when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of inter- est, which is then discharged into the test device through a 1.5k ? resistor. v l/ v cc v cc/ v l iv cc /iv l ov l /ov cc 5k ? 75k ? 5k ? inverter 4 5k ? inverter 3 inverter 2 inverter 1 n one-shot open-drain compatible input cmos- compatible input 230kbps open-drain-to-cmos unidirectional level translator v in where, v s = v cc or v l v th_in / r in1 (v s - v th_in ) / r in2 i in v s r in1 = r in2 = 5k ? for cmos-to-cmos translators r in1 = 75k ? for od-to-cmos translators 0 v th_in figure 8. architecture of 230kbps, od-to-cmos unidirectional translator figure 9. typical i in vs. v in
max13000e?ax13005e iec 61000-4-2 standard esd protection the iec 61000-4-2 standard (figure 12) specifies esd tolerance for electronic systems. the iec61000-4-2 model specifies a 150pf capacitor that is discharged into the device through a 330 ? resistor. the max13000e?ax13005e? i/o on the v cc side are rated for iec 61000-4-2 standard, (8kv contact discharge and ?0kv air-gap discharge). the iec 61000-4-2 model discharges higher peak cur- rent and more energy than the hbm due to the lower series resistance and larger capacitor. applications information power-supply decoupling to reduce ripple and the chance of transmitting incor- rect data, bypass v l and v cc to ground with a 0.1? capacitor. to ensure full ?5kv esd protection, bypass v cc to ground with a 1? capacitor. place all capaci- tors as close to the power-supply inputs as possible. ucsp package considerations for general ucsp package information and pc layout considerations, please refer to maxim application note: wafer-level chip-scale package. ucsp reliability the chip-scale package (ucsp) represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical relia- bility tests. ucsp reliability is integrally linked to the user? assembly methods, circuit board material, and usage environment. the user should closely review these areas when considering use of a ucsp package. performance through operating life test and moisture resistance remains uncompromised as it is primarily determined by the wafer-fabrication process. mechanical stress performance is a greater considera- tion for a ucsp package. ucsps are attached through direct solder contact to the user? pc board, foregoing the inherent stress relief of a packaged product lead frame. solder joint contact integrity must be consid- ered. information on maxim? qualification plan, test data, and recommendations are detailed in the ucsp application note, which can be found on maxim? web- site at www.maxim-ic.com. ultra-low-voltage level translators 18 ______________________________________________________________________________________ high- voltage dc source device under test r c 1m ? r d 1500 ? charge-current- limit resistor discharge resistance storage capacitor c s 100pf figure 10. human body esd test model charge-current- limit resistor discharge resistance storage capacitor c s 150pf r c 50 ? to 100 ? r d 330 ? high- voltage dc source device under test figure 12. iec 61000-4-2 contact discharge test model 100% 90% 36.8% t rl t dl time current waveform peak-to-peak ringing (not drawn to scale) 10% 0 0 amperes i p i r figure 11. human body current waveform
max13000e?ax13005e ultra-low-voltage level translators ______________________________________________________________________________________ 19 functional diagram max13000e?ax13005e v l v cc en i/ov l 1 i/ov l 2 i/ov l 3 i/ov l 4 i/ov l 5 i/ov l 6 i/ov cc 6 i/ov cc 5 i/ov cc 4 i/ov cc 3 i/ov cc 2 i/ov cc 1 gnd
max13000e?ax13005e ultra-low-voltage level translators 20 ______________________________________________________________________________________ typical operating circuits max13001e max13004e +0.9v 0.1 f1 f +2.8v +0.9v system controller +2.8v system data5 data6 data1 data3 data4 data2 data6 data1 data2 data3 data4 data5 gnd v l v cc iv cc_ 6 iv cc_ 5 iv cc_ 4 iv cc_ 3 iv cc_ 2 iv cc_ 1 ov l_ 1 ov l_ 2 ov l_ 3 ov l_ 4 ov l_ 5 ov l_ 6 en max13002e max13005e +0.9v 0.1 f1 f +2.8v +0.9v system controller +2.8v system data5 data6 data1 data3 data4 data2 data6 data1 data2 data3 data4 data5 gnd v l v cc ov cc_ 6 ov cc_ 5 ov cc_ 4 ov cc_ 3 ov cc_ 2 ov cc_ 1 iv l_ 1 iv l_ 2 iv l_ 3 iv l_ 4 iv l_ 5 iv l_ 6 en
max13000e?ax13005e ultra-low-voltage level translators ______________________________________________________________________________________ 21 typical operating circuits (continued) max13000e max13003e +0.9v 1 f +2.8v +0.9v system controller +2.8v system data5 data6 data1 data3 data4 data2 data6 data1 data2 data3 data4 data5 gnd v l v cc i/ov cc_ 6 i/ov cc_ 5 i/ov cc_ 4 i/ov cc_ 3 i/ov cc_ 2 i/ov cc_ 1 i/ov l_ 1 i/ov l_ 2 i/ov l_ 3 i/ov l_ 4 i/ov l_ 5 i/ov l_ 6 en 0.1 f selector guide part data rate (bps) number of bidirectional translators number of v l v cc translators number of v cc v l translators translator configuration max13000e 230k 6 cmos-to-cmos max13001e 230k 6 od-to-cmos max13002e 230k 6 od-to-cmos max13003e 20m 6 cmos-to-cmos max13004e 20m 6 od-to-cmos max13005e 20m 6 od-to-cmos
i/ov cc 3 16 i/ov cc 1 15 i/ov cc 2 14 i/ov cc 4 13 v cc 12 gnd 11 i/ov cc 6 10 i/ov cc 5 9 5 6 7 3 4 8 i/ov l 2 i/ov l 3 1 i/ov l 1 max13000e max13003e tssop 2 en i/ov l 4 v l i/ov l 5 i/ov l 6 top view iv cc 3 16 iv cc 1 15 iv cc 2 14 iv cc 4 13 v cc 12 gnd 11 iv cc 6 10 iv cc 5 9 5 6 7 3 4 8 ov l 2 ov l 3 1 ov l 1 max13001e max13004e tssop 2 en ov l 4 v l ov l 5 ov l 6 ov cc 3 16 ov cc 1 15 ov cc 2 14 ov cc 4 13 v cc 12 gnd 11 ov cc 6 10 ov cc 5 9 5 6 7 3 4 8 iv l 2 iv l 3 1 iv l 1 max13002e max13005e tssop 2 en iv l 4 v l iv l 5 iv l 6 max13000e?ax13005e ultra-low-voltage level translators 22 ______________________________________________________________________________________ bottom view max13001e/max13004e max13002e/max13005e 4 x 4 ucsp v cc gnd iv cc 5 iv cc 4 iv cc 3 1 d c b a 234 iv cc 1iv cc 2 ov l 2 iv cc 6 ov l 1ov l 5ov l 6 ov l 3v l en ov l 4 4 x 4 ucsp v cc gnd ov cc 5 ov cc 4 ov cc 3 1 d c b a 234 ov cc 1ov cc 2 iv l 2 ov cc 6 iv l 1iv l 5iv l 6 iv l 3v l en iv l 4 pin configurations (continued)
max13000e?ax13005e ultra-low-voltage level translators ______________________________________________________________________________________ 23 ordering information (continued) part temp range pin- package max13000eebe-t* -40? to +85? 16 ucsp-16 (4mm 4mm) max13001e eue -40? to +85? 16 tssop max13001eebe-t* -40? to +85? 16 ucsp-16 (4mm 4mm) max13002e eue -40? to +85? 16 tssop max13002eebe-t* -40? to +85? 16 ucsp-16 (4mm 4mm) max13003e eue -40? to +85? 16 tssop max13003eebe-t* -40? to +85? 16 ucsp-16 (4mm 4mm) max13004e eue -40? to +85? 16 tssop max13004eebe-t* -40? to +85? 16 ucsp-16 (4mm 4mm) max13005e eue -40? to +85? 16 tssop max13005eebe-t* -40? to +85? 16 ucsp-16 (4mm 4mm) chip information process: bicmos * future product?ontact factory for availability.
max13000e?ax13005e ultra-low-voltage level translators 24 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) tssop4.40mm.eps package outline, tssop 4.40mm body 21-0066 1 1 g
max13000e?ax13005e ultra-low-voltage level translators maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 25 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) 16l,ucsp.eps h 1 1 21-0101 package outline, 4x4 ucsp

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